1. Field of the Invention
The embodiments of the invention generally relate to p-type metal oxide semiconductor field effect transistors (PFETs) and, more specifically, to a silicon germanium (SiGe), high-k dielectric-metal gate, PFET structure with a reduced threshold voltage (Vt) and a method of forming the structure.
2. Description of the Related Art
As complementary metal oxide semiconductor (CMOS) devices are scaled in size, conventional gate stack structures are being replaced by metal gate stack structures. Specifically, a conventional gate stack structure typically includes a thin silicon oxide (SiO2) gate dielectric layer and a doped-polysilicon gate conductor layer. Unfortunately, doped polysilicon gate conductor layers are subject to depletion effects. These depletion effects result in an increase in the effective gate dielectric layer thickness and, thereby limit device scaling. Thus, high-k dielectric layer-metal gate conductor layer stacks have been introduced. These stacks are improvements over the conventional gate stack structures in that the high-k-dielectric layer minimizes leakage current and the metal gate conductor layer is not subject to depletion effects. However, with ever smaller device sizes new concerns for future CMOS technology generations and, more particularly, for CMOS technology generations at or beyond the 65 nm node are introduced even with such high-k dielectric layer-metal gate conductor layer stacks. For example, the ability to control threshold voltage (Vt) in such devices is critical for device performance and such control has proved difficult, particularly in PFETs which suffer from high Vt. Therefore, there is a need in the art for PFET structure having an optimal Vt and method of forming the structure.